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AMD Design and Verification Engineer interview questions

based on 37 ratings - Updated Jun 26, 2026

Average interview difficulty

Very positive interview experience

How others got an interview

54%
Applied online
Applied online
25%
Campus Recruiting
Campus Recruiting
14%
Employee Referral
Employee Referral
4%
Other
Other
4%
Staffing Agency
Staffing Agency

Interview search

37 interviews

Design Verification Engineer Interview

Mar 9, 2023

Anonymous Interview Candidate

No offer

Positive experience

Difficult interview

Application

I applied online. The process took 4 weeks. I interviewed at AMD

Interview

First a technical screening (45 mins) followed by Full-Panel (4 interviews of 45 mins each), process took around 1 month. The team members kept me updated on the application status.

Interview questions [1]

Question 1

Technical Screening: Q: I was asked about basic programming questions like Leet Code (easy) but mostly based on array, hash-maps, strings and also resume discussion Full-Panel: Q: SystemVerilog constraints, fork-join, mailbox and semaphores based questions Q: Was asked to write scoreboard for a Asynchronous FIFO Q: Monitor and scoreboard code for an AXI write transaction (project based) Q: Resume based discussions Q: Some basic programming problems in language of preference

Answer question

Design Verification Engineer Interview

Aug 16, 2022

Anonymous Interview Candidate

No offer

Positive experience

Average interview

Application

I applied through an employee referral. The process took 2 weeks. I interviewed at AMD (Austin, TX) in Jul 2022

Interview

I was referred and was reached out to in 3 days. Interview consisted of your generic behavioral questions and some technical questions. I was applying for entry level. My advice, please try to get an internship in DV or ask for projects in DV at school.

Interview questions [3]

Question 1

An arbiter with an asynchronous reset receives four requests signals, R1, R2, R3, R4 and generates four grant signals, G1, G2, G3, G4. Request R1 has the highest priority and request R4 has the lowest priority. Draw the state diagram.

2 Answers

Question 2

Draw a count to 5 counter logic circuit.

1 Answer

Question 3

Generate a 2Ghz clock and code the FSM (The one with the asynchronous reset) in verilog.

1 Answer

Design Verification Engineer Interview

Feb 4, 2022

Anonymous Interview Candidate

Declined offer

Positive experience

Difficult interview

Application

I applied online. I interviewed at AMD (Marlborough, MA) in Nov 2021

Interview

2 screening rounds(academic and professional projects, FSM design, SV assertions) on MS Team and 5 final rounds of interview in 1 day (concepts on verilog, SV, UVM, comp arch, C++ coding, Logic design)

Interview questions [1]

Question 1

C++ coding for LRU policy in cache memory design

Answer question

Viewing 21 - 25 of 37 Interviews

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AMD interviews AMD Design and Verification Engineer interviews

Design Verification Engineer Interview

Mar 9, 2023

Anonymous Interview Candidate

No offer

Positive experience

Difficult interview

Application

I applied online. The process took 4 weeks. I interviewed at AMD

Interview

First a technical screening (45 mins) followed by Full-Panel (4 interviews of 45 mins each), process took around 1 month. The team members kept me updated on the application status.

Interview questions [1]

Question 1

Answer question

Design Verification Engineer Interview

Aug 16, 2022

Anonymous Interview Candidate

No offer

Positive experience

Average interview

Application

I applied through an employee referral. The process took 2 weeks. I interviewed at AMD (Austin, TX) in Jul 2022

Interview

Interview questions [3]

Question 1

2 Answers

Question 2

Draw a count to 5 counter logic circuit.

1 Answer

Question 3

Generate a 2Ghz clock and code the FSM (The one with the asynchronous reset) in verilog.

1 Answer

Design Verification Engineer Interview

Feb 4, 2022

Anonymous Interview Candidate

Declined offer

Positive experience

Difficult interview

Application

I applied online. I interviewed at AMD (Marlborough, MA) in Nov 2021

Interview

Interview questions [1]

Question 1

C++ coding for LRU policy in cache memory design

Answer question

AMD

AMD Design and Verification Engineer interview questions

Average interview difficulty

Very positive interview experience

How others got an interview

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Design Verification Engineer Interview

Design Verification Engineer Interview

Design Verification Engineer Interview

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Design Verification Engineer Interview

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