I applied through an employee referral. I interviewed at AMD (Bengaluru) in Mar 2024
Interview
Phone screening round at AMD for Design Verification Engineer position. Main focus areas for the role include Advanced Computer Architecture, Verilog / SV, Digital Design, Python / C / C++
Interview questions [1]
Question 1
Coding questions - Python - sort a list and check if number is palindrome
Logic puzzle
Behavioral questions based on previous work experience
I applied through an employee referral. I interviewed at AMD in Mar 2026
Interview
Applied to AMD (Xilinx) for a Senior/Staff DV role. The overall experience was a complete let down, the hiring process does not match the big name reputation AMD is having.
Round 1 is HR screening which was very quick and smooth. Round 2 is a take-home assignment with 3-day duration. And I had to wait for 1.5 months to get processed for round 3, which was still acceptable.
Round 3 is technical session where I wrote code and then explained my solutions. The questions were very easy for senior perspective, and I think it's a one-way path where there was only 1 right answer. And these codes are overlap with the take-home assignment.
However, I got ghosted for 2 months. Regardless many follow-up messages, nothing but silence.
When I moved on with another offer, I sent a personal message to the interviewer telling him my decision. Only then I got informed that my solutions were "too much" and hence a rejection.
A fellow of mine (who is 2y older) got selected for the role. He shared that the compensation was way bellow online surveys and national average.
* To sum up my thoughts
-> a waste of time: totally 4 months spent (1-2 months between rounds). Only SystemVerilog tested. I already completed the take-home but had to rewrite the codes in the interview. No leadership, no soft skills, no asking about previous impacts and achievements, just boring codes.
-> low standard: AMD is a big name, so I thought expectations should be held high. But not with the team I'm joining. Getting rejected for "being too much" at a name like AMD is kinda unexpected.
-> the hiring team should rework the input-level, go out side and see what's the market doing. Bland lines of coding and proving it gonna work does not make a staff/senior dv engineer, it's junior, and the pay is junior. But the JD stated Snr/Staff. Yikes!
-> And the JD is actually recruiting juniors making me sickly personal.
Interview questions [1]
Question 1
Write a APB outstanding-transaction driver function in UVM.
campus interview . 2 rounds, basic questions from STA , cmos, digital basics , verilog questions, verilog code for asynchronus d flipflop, blocking and non blocking statements, structure of 3 input OR gate, explain about static and dynamic power
1. HR Screen
2. Technical Round
The whole process was around 2 weeks.
You first get a call from the HR and then will answer questions.
If you are successful, you will book a time for a technical interview.
Interview questions [1]
Question 1
Tell me the difference between combinational and sequential logic