Static timing analysis, setup time, hold time, verilog questions, puzzles, clock domain crossing, synchronisation
Asic Design Engineer Interview Questions
1,317 asic design engineer interview questions shared by candidates
The standard, how to design an async FIFO?
If your constraint block includes values like 0, 1, 4, and 300 to 400, how would you handle that in coverage?
Tell me more about your projects.
Told to design a layout through a very slow laptop, be prepared. asked about parasitics in layout design, and effect of high voltage on MOS and what should you do.
Previous challenges as a physical design engineer, lot of questions about the .libs and encounter commands.
Scripting skills in Perl : regular expressions Logical Effort, Projects done in Master's
Given a diagram, how would you verify a design/check output data. Computer arch basics and design questions
system verilog, static timing analysis
functional, code coverage ,priority encoder explanation, SV
Viewing 1191 - 1200 interview questions