What will gm change if we enlarge the W/L of a transistor by 2. Compare the gm of a BJT and MOS device. Slew rate problem
Asic Design Engineer Interview Questions
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Retiming for a 5 input OR
FIFO Design
Sequence detecting FSM, coding it in Verilog
Design Questions and some logic questions
Logical design, physical design, perl, System verilog (UVM)
Questions in digital design, timing violations, metastability
It's about a clock frequency problem, something related to time borrowing.
CDC and metastability and ways to implement synchronizer in circuit, also how to use asynchronous FIFO and the logic goes in building FIFO
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