One hot encoding, FSM divide by 3, Verilog coding.
Asic Design Engineer Interview Questions
1,316 asic design engineer interview questions shared by candidates
Read after write sequence implementation
General questions about caches / memory systems.
write assertions to verify the condition.
They asked about click domain crossing what do I know?
Standard digital design questions: 1. FSM 2. Multiplier design/questions 3. sync vs async reset
Cache coherency, mapping techniques, metastability, cdc, synchronizers,
Delay analyst for latches and how to decrease the delay and clock period.
1. explain synthesis flow in ASIC 2. Explain STA and what tools do you use 3. significance of physically aware netlist over regular netlist 4. explain setup and hold time 5. how will you solve critical path problems using PT
Design sequence detector with logic circuit diagram
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