Virtual memory and paging, details of reservation stations, load store ordering, cache org, role of design verif and how do you interact with them.
Cpu Design Engineer Interview Questions
222 cpu design engineer interview questions shared by candidates
Pipelining, latency and throughput, Cache, types of cache, problem on set way associative cache, interrupts, Virtual memory, page fault, project.
one-hot assignment in verilog
Explain how an out-of-order processor works? How do you implement register renaming? Difference between an architectural and physical register file
What is one time where you had experienced a stressful situation and how did you handle it?
On-campus: Verilog code writing, simple hardware design question using muxes and counter that was approached from different levels of abstraction. Phone Interview: Entirely computer architecture questions, including cache coherency protocols, cache organizations
Q: Register renaming. How it works
What year are you in university, and what are you doing?
Out of order processor, importance ILP (and it's advantages), Digital design (realizing basic gates with a MUX)
How do you think you will fit in?
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