What are the hazards in a pipelined processors and how to rectify them?
Cpu Design Engineer Interview Questions
222 cpu design engineer interview questions shared by candidates
Describe a situation when you would use a Direct mapped cache over a set associative cache.
Telephonic interview Architecture basics Cache coherence and Coherency protocols, Banking System, Multithreading, Operating system basics - race condition, mutex, semaphores, virtual memory, paging, fragmentation
do swap without using variables
Regarding CPU Clock Signals and Timing Analysis.
C++ Questions, memory allocation
What are some ways for error testing/handling in software?
compare tradeoffs of 10 wide vs. 4x 2.5 wide parallel transistors. Made me think.
Why there is a E stage in MESI protocol, I said I don't know, will you please teach me that? He said, NO.
Tomasulo project
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