tell about what you did in you last job, what you were responsible for
Design Verification Engineer Interview Questions
3,719 design verification engineer interview questions shared by candidates
Read the RTL code and point any errors that you can find
implement blackjack with classes in python
How would you test a component that splits the memory for 8 different data streams
Then asks questions in SV & UVM starting from basic concepts to transaction level modelling & even asks you to develop a UVC for a protocol.
Not Applicable and confidential as per norms
C++ encapsulation, inheritance and polymorphism
Nothing was unexpected, very minimal behavioral questions. All the technical questions are regarding to computer architecture subjects.
ask the concept of virtual function, pure function in c++. Ask previous verification experience. An question about how to write a c program to judge whether a machine is big-endian or little-endian
Given read and write freq, how to calculate FIFO depth?
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