1. constraints 2. assertions 3. UVM topology
Design Verification Engineer Interview Questions
3,719 design verification engineer interview questions shared by candidates
Tech Interview: Basic Questions like Lifo Fifo, Stack Queues, Logic Gates HR Interview: About myself, Job expectation, Other Interests
tlm and its benefits. difference between blocking and nonblocking transactions
detailed test plan for a synchronous fifo
Uvm phases and explain them
Strong focus on making sure Veriff and the candidate are on the same page in terms of values, future goals etc. (for example - relation to Veriff's mission)
Basic CMOS Physical design related Sta Tool related
MATLAB functions, DSP related questions;
Introduce yourself and tell us something unique about you.
Tell me about your previous experience.
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