Strong focus on making sure Veriff and the candidate are on the same page in terms of values, future goals etc. (for example - relation to Veriff's mission)
Design Verification Interview Questions
3,721 design verification interview questions shared by candidates
Introduce yourself and tell us something unique about you.
Tell me about yourself
Tell me about your background What are your aspirations in life? Why would you like to work with such a company? Tell us about an experience where you used your skills in your previous job.
About digital electronics for VLSI domain
What is TLB cache? Why is it used?
A general question that sees how is my verification thinking. Since I had no previous experience with verification, it took my a little while to understand what was asked.
Questions about past experience with Verilog and VHDL
Why modport is used? What is polymorphism? What is deep copying ? what is inheritence? Why we are writing interface? Different Phases in UVM? Which phase are task and which are functions?
It was a quetion about linked lists.
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