Design basic logic gates (AND, XOR) using a 2to1 mux. Write a module which will take clk as an input and output a clk divided by 3. Important to note that generated clock needs to be an output of the Flop.
Digital Asic Design Engineer Interview Questions
53 digital asic design engineer interview questions shared by candidates
RTL coding related questions such as writing a simple FSM.
How can I estimate a new IP complexity and area without having any specific details yet?
Intro and things worked on. Then he asked me deep about the project I was working on. Synchronous FIFO question. Wrote for 50 continuous cycle s in any 100 cycles but reading every alternate cycles. Depth reqd? How to design synch fifo ? How async fifo ? Is it possible to write and read from sync FIFO built using single port sram in same clock cycle ? Setup time and why we need it ? How will multiply by 63 ? Optimize way of finding the square of a number ? 1, 4, 9, 16, 25,
Clock domain crossings and reset domain crossings
Wie funktionieren Flip Flops? Wie funktioniert SerDes?
Explain how to build an inverter with CMOS components.
Design a filter with gain x at DC and gain y at infinite frequency. Now adjust it so that gain at infinite frequency is y'.
What is a fpga and what is a lookup table?
Some code test. Some system knowledge test.
Viewing 31 - 40 interview questions