Ex: "aaab", 2 => "aab" Ex: "aabb", 1 => "ab" Ex: "aabbaa", 1 => "aba" Ex: "aaaabbaa", 3 => "aaabbaa" Ex: "aaaabbaa", 1 => "aba" Ex: "abcd", 1 => "abcd
Fpga Design Engineer Interview Questions
681 fpga design engineer interview questions shared by candidates
How do you find the equivalent resistance of this infinite resistor mesh?
Where can you meet and how can you solve the hold time violation?
Delay the bus signal with BRAM.
Where can you meet and how can you solve the hold time violation?
design a module using any HDL that recives pulses and the goal is to detect 10 pulses within 100 cycles, the interesting part is the ability to detect 10 ulses from the moment we get each pulse. for example: lets say we get a pulse start counting the 100 cycles, if we reach 10 pulses before the time ends then start counting from the time we received the second pulse until the eleventh and so on.
Introduce yourself please .what is carrier goal
About ethernet communication and timing system.
Take home VHDL coding assignment
Here is a diagram of a control system, what aspects would you need to think about when considering a fail-safe approach?
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