How to design a UVM testbench for a given design. What all componets are needed etc. Corner cases to test out and efficient way to build environment
Senior Verification Engineer Interview Questions
192 senior verification engineer interview questions shared by candidates
First round: 1) Introduction on your experience, the job profile requirement and your motivation. DIscussion our application and CV. Second Round: 1) Technical questions on the projects you worked on. This will be in details. Both simulation based ( SV/UVM) and formal methods were discussed. Third round (HR): 1) very generic HR questions like, tell me about your self, your strengths/weakness, motivation to join Synopsys, what your team will say about you . describe a conflicting situation you handled, how do you keep your team motivated, salary expectations and personal situation etc.
mentioned above in detail .. ..
Write TB for one of the projects from past experience . Describe its features and implement DUT interface connections and build TB on whiteboard .
Cache Coherency, UVM and TLM related, SV concepts, Past projects.
Sv and UVM project knowledge protocol mentioned in CV
Conceptual knowledge of SV and UVM was tested
What is the difference between local, protected and publice. Give an example usage of the three.
How would you do your job in X project?
Verification related questions.
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