Draw out the circuit simple verilog code would synthesize to
Verification Manager Interview Questions
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Uvm phases and explain them
Tech Interview: Basic Questions like Lifo Fifo, Stack Queues, Logic Gates HR Interview: About myself, Job expectation, Other Interests
Question on Project, tool awareness, uvm methodology, driver code and testplan development.
How would you use a DMM (digital multimeter) to debug hardware?
tlm and its benefits. difference between blocking and nonblocking transactions
detailed test plan for a synchronous fifo
write a code,a task to fill an array[x][y] ?
What is polymorphism, how is it different from inheritance, give an example usage of polymorphism in Systemverilog testbench generation.
How competent are you with analysis tools such as Excel?
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