set up time and hold time
Vlsi Engineer Interview Questions
305 vlsi engineer interview questions shared by candidates
Basics of C language, Detailed explaination of projects
Basic vlsi questions , project questions
How do you replace cat with dog in perl?
What happens if you don't give a default statement? How is latch inferring bad for the design?
there were many questions on basic verilog and vlsi which i dont knew.
whats rtl level designing in verilog
What is MAC/PHY?
Basics of Verilog and system Verilog
All STA, Physical Design, timing power optimization questions. C++ , perl knowledge required
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