Given read and write freq, how to calculate FIFO depth?
Design Verification Engineer Interview Questions
3,720 design verification engineer interview questions shared by candidates
Most of the questions were about my projects and basic questions regarding them like UART, FIFO , basic digital design questions, System verilog questions
How to convert hexadecimal to decimal.
Design a circuit that takes 4 bit BCD as input and has the input times 5 as output
Draw a NAND using cmos gates
system verilog constraints interview questions
- about SV, FIFO design, arbiter design
Basics of sv, sva, verilog
It was a quetion about linked lists.
It was a quetion about pysical memroy.
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