Digital basics, Verilog coding and Questions realated to Resume
Rtl Design Interview Questions
275 rtl design interview questions shared by candidates
Core subjects, digital electronics, cmos, verilog
Explain and design a two level branch predictor
What's hash? what's link list?
What's setup and hold time? How to solve the setup and hold violaton.
another tough question was that you are given a small design, you are asked to tell how you test that logic. like how/what checkers to implement.
What is fifo
FIFO fundamentals (synchronous) and depth calculation, arbiter fundamentals (fixed priority, round robin, weighted), experience with cache, how to optimize a given logic path for timing assuming area is no concern, my ASIC design experience (timing closure, microarchitecture, block explanations).
FIFO depth
nothing as such..everything was from what i had studied in BS and MS
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